ChangXin Memory Technologies (长鑫存储), core subsidiary of 长鑫科技, expects to launch a new-generation DDR5 RDIMM product using its 4F² DRAM architecture by the end of 2026. President Cao Kanyu (曹堪宇) outlined the architecture at the Fourth Integrated Chip and Die Conference on 10 October, identifying the VSG (Vertical Surrounded Gate) transistor and more than 300 related published patent families as the basis for the plan. The product is positioned as the first application of the architecture and as an entry into the server memory segment.
Who this affects
- For exporters: The statement identifies the DDR5 RDIMM as the first-generation product on the 4F² architecture, targeted at the server memory market where overseas vendors have held long-term advantages.
- For investors: Cao Kanyu stated that the company holds more than 300 published patent families related to the 4F² architecture, described as industry-leading in number.
- For counsel/compliance: The architecture is described as innovating on DRAM storage-array transistors via the self-developed VSG vertical surrounded-channel structure to address leakage and short-channel effects.
- For policymakers: The plan moves a Chinese DRAM producer into the server segment previously weighted toward consumer electronics in its downstream business.
The read
The 10 October statement places the first commercial application of CXMT’s 4F² work directly into the highest-reliability DRAM product category rather than a consumer or mobile derivative. The architecture is presented as a shift from 2D transistor design—where array and peripheral logic shared the same lithography and doping conditions—to a 3D approach that decouples DRAM and CMOS processes and uses wafer-level hybrid bonding. This is the documented pattern of moving from research disclosures to a stated product target in a segment that requires continuous operation, thermal-plug tolerance, and multi-vendor compatibility.
What was the action?
President Cao Kanyu of 长鑫存储 stated at the Fourth Integrated Chip and Die Conference on 10 October that the company expects to launch a new-generation DDR5 RDIMM product using its 4F² DRAM architecture by the end of the year. He described the architecture as innovating on the transistors in the DRAM storage array through the self-developed VSG (Vertical Surrounded Gate) transistor, which uses a vertical surrounded-channel structure.
What’s the penalty / scope, and how is it set?
No penalty is stated. The action is a product launch plan: the first-generation product on the 4F² architecture is set as a DDR5 RDIMM for the server memory market. The scope is the application of the denser cell architecture (each unit occupying 4 times the square of the minimum feature size versus the mainstream 6F²) together with process decoupling and wafer-level hybrid bonding to address manufacturing bottlenecks.
Who else is exposed?
The statement identifies overseas storage vendors as having held long-term advantages in the server memory field. It notes that 长鑫存储’s downstream business previously focused on consumer electronics. No other specific companies, customers, or process nodes are named.
What happens next
The stated timeline is a product launch by the end of 2026. The open question is whether the DDR5 RDIMM clears the reliability, compatibility, and continuous-operation requirements of the server segment that the statement itself identifies as higher-difficulty than consumer memory.